1. Technical Field
The present invention relates generally to semiconductor technology, and more specifically to solid phase epitaxy damage control in semiconductor devices.
2. Background Art
At the present time, electronic products are used in almost every aspect of life, and the heart of these electronic products is the integrated circuit. Integrated circuits are used in everything from airplanes and televisions to wristwatches.
Integrated circuits are made in and on silicon wafers by extremely complex systems that require the coordination of hundreds or even thousands of precisely controlled processes to produce a finished semiconductor wafer. Each finished semiconductor wafer has hundreds to tens of thousands of integrated circuits, each wafer worth hundreds or thousands of dollars.
Integrated circuits are made up of hundreds to millions of individual components. One common component is the semiconductor transistor. The most common and important semiconductor technology presently used is silicon-based, and the most preferred silicon-based semiconductor device is a Complementary Metal Oxide Semiconductor (“CMOS”) transistor.
The principal elements of a CMOS transistor generally consist of a silicon substrate having shallow trench oxide isolation regions cordoning off transistor areas. The transistor areas contain polysilicon gates on silicon oxide gates, or gate oxides, over the silicon substrate. The silicon substrate on both sides of the polysilicon gate is slightly doped to become conductive. These lightly doped regions of the silicon substrate are referred to as “shallow source/drain junctions”, which are separated by a channel region beneath the polysilicon gate. A curved silicon oxide or silicon nitride spacer, referred to as a “sidewall spacer”, on the sides of the polysilicon gate allows deposition of additional doping to form more heavily doped regions of the shallow source/drain (“S/D”) junctions, which are called “deep S/D junctions”.
To complete the transistor, a silicon oxide dielectric layer is deposited to cover the polysilicon gate, the curved spacer, and the silicon substrate. To provide electrical connections for the transistor, openings are etched in the silicon oxide dielectric layer to the polysilicon gate and the S/D junctions. The openings are filled with metal to form electrical contacts. To complete the integrated circuits, the contacts are connected to additional levels of wiring in additional levels of dielectric material to the outside of the dielectric material.
In operation, an input signal to the gate contact to the polysilicon gate controls the flow of electric current from one S/D contact through one S/D junction through the channel to the other S/D junction and to the other S/D contact.
Transistors are fabricated by thermally growing a gate oxide layer on the silicon substrate of a semiconductor wafer and forming a polysilicon layer over the gate oxide layer. The oxide layer and polysilicon layer are patterned and etched to form the gate oxides and polysilicon gates, respectively. The gate oxides and polysilicon gates in turn are used as masks to form the shallow S/D regions by ion implantation of boron or phosphorus impurity atoms into the surface of the silicon substrate. The ion implantation is followed by a high-temperature anneal above 700° C. to activate the implanted impurity atoms to form the shallow S/D junctions.
A silicon nitride layer is deposited and etched to form sidewall spacers around the side surfaces of the gate oxides and polysilicon gates. The sidewall spacers, the gate oxides, and the polysilicon gates are used as masks for the conventional S/D regions by ion implantation of boron or phosphorus impurity atoms into the surface of the silicon substrate into and through the shallow S/D junctions. The ion implantation is again followed by a high-temperature anneal above 700° C. to activate the implanted impurity atoms to form the S/D junctions.
After formation of the transistors, a silicon oxide dielectric layer is deposited over the transistors and contact openings are etched down to the S/D junctions and to the polysilicon gates. The contact openings are then filled with a conductive metal and interconnected by formation of conductive wires in other interlayer dielectric (“ILD”) layers.
As transistors have decreased in size, it has been found that the electrical resistance between the metal contacts and the silicon substrate or the polysilicon has increased to the level where it negatively impacts the performance of the transistors. To lower the electrical resistance, a transition material is formed between the metal contacts and the silicon substrate or the polysilicon. The best transition materials have been found to be cobalt silicide (CoSi2) and titanium silicide (TiSi2).
The silicides are formed by first applying a thin layer of the cobalt or titanium on the silicon substrate above the S/D junctions and the polysilicon gates. The semiconductor wafer is subjected to one or more annealing steps at temperatures above 800° C., and this causes the cobalt or titanium to selectively react with the silicon and the polysilicon to form the metal silicide. The process is generally referred to as “siliciding”. Since the shallow trench oxide and the sidewall spacers will not react to form a silicide, the silicides are aligned over the S/D junctions and the polysilicon gates so the process is also referred to as “self-aligned siliciding”, or “saliciding”.
As the dimensions of polysilicon gates continue to shrink, the so-called “narrow line” effect becomes a major concern in producing high quality, self-aligned silicide layers. The narrow line effect refers to problems due to the reduction in gate dimensions. With small gate dimensions, too much stress may accumulate at the interface between the polysilicon gate and the metal silicide layer. In addition, there may be too few nucleation sites on the original gate surface for forming a high quality metal silicide layer. This leads to an increase in sheet resistance that may adversely affect the operation of the transistor gate.
Therefore, in the fabrication of semiconductor devices having a line width smaller than, for example, 0.25 μm, a pre-amorphization implant (“PAI”) is frequently carried out first. The PAI is an implant that creates a layer of amorphous silicon at the top of the polysilicon gate and the S/D regions of the transistor, so that a subsequent self-aligned silicide process can produce a metal silicide layer having a lower sheet resistance.
PAI is also valuable for other purposes. For example, ion implantation of energetic impurity atoms into a silicon substrate to change its electronic properties is common in the electronics industry. For an ion-implanted impurity to be electrically active, it must be located in substitutional sites in the crystal lattice of the surface layer of the substrate. To cause the implant to become substitutional and electrically active, an annealing process is performed.
The ion implantation of the impurity atoms occurs prior to the annealing process. If the ion implantation energy of the impurity atoms is sufficient, it can damage the silicon substrate enough to amorphize the surface of the silicon substrate. If the damage is sufficient, lower annealing temperatures (e.g., 900° C. or less) may be adequate to produce sufficient regrowth of the amorphized silicon by solid-phase epitaxy (“SPE”) to restore the surface of the silicon substrate with minimal crystal defects. It may also be sufficient to locate the implanted ions properly in substitutional sites.
Such lower annealing temperatures are desirable to limit implant migration and to preserve implantation profiles. However, a low-dose impurity ion implant, e.g. below about 1015 ions/cm2 of phosphorus, arsenic, or boron, will not typically produce the desired degree of damage in the silicon substrate to warrant the use of lower annealing temperatures.
To compensate, a PAI can be used to amorphize the surface of the silicon and create the additional damage necessary for an impurity ion implant to become substitutional at lower annealing temperatures. Such a PAI is generally carried out with inert ions such as silicon, neon, or argon, although it is known that any atom can be used to amorphize silicon.
During the subsequent annealing process, the healing of such ion implant-induced damage is the result of epitaxial growth through SPE, during which the amorphous silicon is recrystallized into the form of monocrystalline silicon.
SPE has also been used to form abrupt and shallow S/D extensions. PAI can be performed prior to the SPE formation of such extensions to achieve better activation during recrystallization of the SPE. However, the SPE process can leave residual damage along the path of the electrical current in the transistor. For example, such defects can leave amorphous layers between the silicon oxide and the silicon. The residual damage will then degrade the performance of the transistor device.
A long felt need therefore remains for improvements to such SPE processes that will remove such defects without necessitating the use of higher annealing temperatures.
Solutions to these problems have been long sought but prior developments have not taught or suggested any solutions and, thus, solutions to these problems have long eluded those skilled in the art.